The present invention relates to a method for fabricating a semiconductor device and, more particularly, to a method for fabricating a semiconductor device with an ultra-shallow epi-channel of which the channel length is 100 nm or less.
Generally, in transistors such as MOSFETs or MISFETs, the surface area of a semiconductive substrate, which is disposed below a gate electrode and a gate dielectic layer, functions to allow the currents to flow due to the electric field applied to source/drain in a state that a voltage beyond the triggering is applied to the gate electrode. Therefore, this area is called xe2x80x9cchannelxe2x80x9d.
In addition, characteristics of these transistors are determined by the dopant concentration of the channel. Accurate doping of the channel is very important since the general properties such as threshold voltage (VT) and drain currents (Id) of a transistor are determined by the dopant concentration.
As a doping method of the channel, channel ion implantation (or threshold voltage adjusting ion implantation) using ion implantation method are widely used. The channel structures that can be formed using the above ion implantation method include a flat channel having a constant concentration within a channel in depth, the buried channel formed the channel at a specific depth away from the surface, the retrograde channel having a low surface concentration and whose concentration within the channel increases rapidly in a depth direction, etc.
Among the above channels, the retrograde channel is widely used in a high performance microprocessor of which the channel length is 0.2 m or less. The retrograde channel is formed using heavy ion implantation of In, As, Sb, etc. Since the retrograde channel has high surface mobility due to the low surface dopant concentration, it has been applied to high performance devices with high driving current characteristics.
However, with decreasing the channel length, the required channel depth must be shallower. Also, the ion implantation techniques have limitations when implementing on the formation of retrograde channel of which the channel depth becomes 50 nm or less.
In order to meet these demands, there has been proposed the epi-channel structure in which an epitaxial layer is formed on a channel doping layer.
FIG. 1A is a cross-sectional diagram of a semiconductor device with a conventional epi-channel structure.
Referring to FIG. 1A, a gate dielectric layer 12 and a gate electrode 13 are formed on a semiconductive substrate 11, and the epi-channel consisting of an epitaxial layer 14 and a channel doping layer 15 is formed on the semiconductive substrate 11 disposed below the gate dielectric layer 12. A high-concentration source/drain extension (SDE) region 16 and a source/drain region 17 are formed on both sides of the epi-channel.
However, since it is difficult to control dopant loss and diffusion of the channel doping layer 15 due to the process of forming the epitaxial layer and the following thermal process, there is a problem to implement the improved on/off current characteristic required for the high performance device with the epi-channel structure.
In order to solve this problem, there has been proposed a method for implementing a delta doped epi-channel by forming a dual epitaxial layer consisting of a doped epitaxial layer doped in a step shape and an undoped epitaxial layer, as shown in FIG. 1B.
FIG. 1B shows the change of a doping profile according to the transient enhanced diffusion (TED) or the thermal budget, followed by the forming of the delta doped epi-channel. Referring to FIG. 1B, since the step-like delta doping profile of the epi-channel below the gate dielectric layer (Gox) does not maintain an ideal delta doping profile (P1) due to the TED or the thermal budget, there occurs the broadening (P2) of the doping profile.
Accordingly, in case where the delta doped epi-channel is formed using the dual epitaxial layer consisting of the doped epitaxial layer and the undoped epitaxial layer, since a low concentration epitaxial layer of 1xc3x971019 atoms/cm3 or less cannot be deposited, the diffusion (D) of dopants due to the TED or the thermal budget is too excessive, so that there is a limitation when implementing the delta doped epi-channel of which the channel depth is 30 nm or less.
In order to improve these problems, there is proposed a method in which after forming a delta doped n-channel doping layer having a precisely controlled concentration by ultra low energy boron ion implantation, laser thermal annealing (LTA) process is instantaneously performed to prevent the diffusion of the delta doped n-channel doping layer (referring to FIGS. 2A and 2B).
FIGS. 2A and 2B are cross-sectional diagrams showing the method for fabricating a semiconductor device with an epi-channel formed by ultra low energy ion implantation and by laser thermal annealing (LTA) process.
As shown in FIG. 2A, a field oxide layer 22 with shallow trench isolation (STI) structure is formed on a semiconductive substrate 21, and P-type dopants are ion-implanted into the semiconductive substrate 21 to thereby form P-type well 23. Sequentially, boron ions are implanted under ultra low energy (1 keV) to form a delta doped channel doping layer 24.
Then, the laser thermal annealing (LTA) process of 0.36 J/cm2 to 0.44 J/cm2 is directly performed without any pre-amorphization for amorphizing a surface of the semiconductor substrate 21. As can be seen in FIG. 2B, the laser thermal annealing process suppress the re-distribution of boron within the channel doping layer 24, as well as changing the channel doping layer 24 into chemically stable channel doping layer 24A.
As shown in FIG. 2B, an epitaxial layer 25 is selectively grown on the channel doping layer 24A at a temperature of 600 to 800 to thereby form the super steep retrograde (SSR) epi-channel structure.
Meanwhile, the TED of the delta doped channel doping layer can be prevented by using rapid thermal annealing (RTA) process as well as the laser thermal annealing process.
FIG. 3A and FIG. 3B are the graphs showing the doping profiles of SSR epi-channel formed by selectively epitaxial growth on boron doped specimens of 1 KeV ion implanted or 5 KeV ion implanted, respectively.
As can be seen from FIGS. 3A and 3B, in the doping profiles of SSR epi-channel formed using the ultra low energy ion implantation, as the ion implantation energy becomes lower, a distribution range of delta doping becomes narrower. Since this delta doping which is narrowly distributed as shown in FIG. 3A can remarkably reduce the junction capacitance of device and the junction leakage current, it is an essential technique in manufacturing the low-power and high-efficiency semiconductor device.
However, the ultra low energy ion implantation has disadvantages that the available energy is limited, since it is difficult to extract enough ion beam currents at such ultra low energy range, as well as the manufacturing time is taken longer.
It is, therefore, an object of the present invention to provide a method for fabricating a semiconductor device with epi-channel structure, which is adapted to overcome an available energy limitation and to improve the productivity by providing the method of SSR epi Channel doping by boron-fluoride compound ion implantation without using ultra low energy ion implantation.
In addition, it is another object of the present invention to provide a method for fabricating the semiconductive device with epi-channel structure adapted to prevent the crystal defects caused by the epitaxial growth on ion bombarded and fluorinated channel doping layer.
In an aspect of the present invention, there is provided a method for forming the epi-channel of a semiconductor device, which comprises the steps of: a) forming a channel doping layer below the surface of a semiconductive substrate by implanting boron-fluoride compound ions containing boron; b) performing the annealing process to remove fluorine ions injected within the channel doping layer; c) performing a surface treatment process to remove the native oxide layer formed on a surface of the channel doping layer and simultaneously remove remaining fluorine ions within the channel doping layer; and d) growing an epitaxial layer on the channel doping layer using the selective epitaxial growth method.
In another aspect of the present invention, there is provided a method for fabricating a semiconductor device, which comprises the steps of: a) forming a channel doping layer below the surface of a semiconductive substrate by to implanting boron-fluoride compound ions containing boron; b) performing the first annealing process to remove fluorine ions, injected during above channel doping implantation, within the channel doping layer; c) performing the surface treatment process to remove the native oxide layer formed on the surface of the channel doping layer and simultaneously remove remaining fluorine ions within the channel doping layer; d) growing the epitaxial layer on the channel doping layer; e) sequentially forming a gate dielectric layer and a gate electrode on the epitaxial layer; f) forming source/drain extension regions arranged at edges of the gate electrode, wherein the source/drain extension region is shallower than the channel doping layer; g) forming spacers contacted with both sides of the gate electrode; h) forming source/drain regions arranged at edges of the spacers of the gate electrode, wherein the source/drain regions are deeper than the channel doping layer; and i) performing the second annealing process, for the activation of dopants contained in the source/drain extension regions and the source/drain regions, at a temperature suppressing the diffusion of the channel doping layer.